The pipeline architecture has become the typical design used in many conventional processors due to higher throughput achievements. In pipelining, a sequence of tasks is followed in order to process instructions, such as fetching instructions, decoding instructions, execution, and storing results which are connected through the means of the pipelines. As instruction flow through the pipeline their tasks are sequentially performed by each stage. Each instruction is followed by its next sequential instruction which will occupy as soon as possible the stations which it vacates the time delay between the initiation of different instructions and the completion thereof under the pipeline architecture is therefore compacted and throughout of the computer is increased. Pipelining inserts a set of ‘pipeline registers’ between combinational units to hold intermediate results at clock boundaries. Typical reduced instruction set computing (RISC) and very long instruction word (VLIW) processors have at least 2-4 pipeline stages between the time a computation is performed in the an arithmetic logic unit (ALU) and the time the resulting value is written into a register file or flip-flop based register bank what is usually known as the write back stage. A register file is found in many data processing units and comprises a plurality of registers. A register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction issue width. A standard solution to increase performance in a processor is to implement what is referred to as register forwarding or register bypassing. This implementation method is a technique that compares the source register indexes of the input operands into the ALU in clock cycle n with the results of previous operations (cycles n-1, n-2, . . . ) that have not yet been committed to the register bank. If there is a match, the value ‘in flight’ to the register bank is used/forwarded or bypassed into the input of the ALU instead of using the value that was read from the register bank temporarily, thus the pipeline registers temporarily are holding these values. Registers are considered live if their value is still expected to be used in a future cycle and when the number of registers live is higher than the number of registers in the micro-processor, the compiler ‘spills’ some of the values held in those registers onto the stack or a temporary storage memory area so that the registers can be used for other purpose. These register spillages degrades performance due to store instruction and subsequent load from the memory.
It is therefore an object of the present invention to provide a novel and unique approach to reduce register pressure in compilers by providing a set of short lived registers at near-zero cost. These extra registers can be beneficial to avoid register spillage that consequently result in degradation in performance. Thus this feature can effectively increase the performance per area metric on a modern micro-processor, save leakage power while reducing activity in the processor, and most importantly save cost.